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Mechanical Engineer III
WR Systems
Dam Neck, VA
WR is seeking a Mechanical Engineer III to lead the design, development, integration, and qualification of electromechanical systems supporting advanced naval platforms.
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Process Engineer
AmeriStaff Inc.
Martinsville, VA
…technical problem-solving across yarn, fabric, and garment applications. The ideal candidate will have a strong background in textile engineering, chemical engineering, or polymer…
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Automated Test Engineer (Edifecs)
Syms Strategic Group, LLC (SSG)
Blacksburg, VA
Syms Strategic Group (SSG) is seeking a talented Automated Test Engineer (Edifecs)
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Automated Test Engineer (MUMPS)
Syms Strategic Group, LLC (SSG)
Blacksburg, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
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Software Developer in Test (SDET)
Syms Strategic Group, LLC (SSG)
Blacksburg, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
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Senior Software Test Engineer
Syms Strategic Group, LLC (SSG)
Blacksburg, VA
Syms Strategic Group (SSG) is seeking a talented Senior Software Test Engineer
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Cyber Systems Engineer (Level 3 or 4)
Northrop Grumman
Dulles, VA
…and/or highly virtualized environments. Prepare Certification To Field (CTF) assessment procedures. Execute CTF test cases for observation by customer cybersecurity…
Added 1 min ago
AWS Engineer
Koniag Government Services
Vienna, VA
Kadiak, LLC, a Koniag Government Services company, is seeking an AWS Engineer with a TS/SCI security clearance to support Kadiak and our government customer in Vienna, VA. This position…
Added 1 min ago
Network Engineer, Operations & Support
Meta
Ashburn, VA
Meta is seeking a Network Engineer to join our Site Services and Edge Network Services (ENS) Operations team. In this role, you will support the deployment, integration, and ongoing…
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Automated Test Engineer (Edifecs)
Syms Strategic Group, LLC (SSG)
Ashburn, VA
Syms Strategic Group (SSG) is seeking a talented Automated Test Engineer (Edifecs)
Added 1 min ago
Automated Test Engineer (MUMPS)
Syms Strategic Group, LLC (SSG)
Ashburn, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
Added 1 min ago
Software Developer in Test (SDET)
Syms Strategic Group, LLC (SSG)
Ashburn, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
Added 1 min ago
Senior Software Test Engineer
Syms Strategic Group, LLC (SSG)
Ashburn, VA
Syms Strategic Group (SSG) is seeking a talented Senior Software Test Engineer
Added 1 min ago
Applications Architect (Enterprise Modernization & Cloud Migration) - (Active Top Secret/SCI Eligibility)
Akima
Alexandria, VA
We are seeking an experienced individual to fill the role of Applications Architect to contribute to the rationalization and modernization of a legacy, complex enterprise application…
Added 1 min ago
Automated Test Engineer (MUMPS)
Syms Strategic Group, LLC (SSG)
Charlottesville, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
Added 1 min ago
Automated Test Engineer (Edifecs)
Syms Strategic Group, LLC (SSG)
Charlottesville, VA
Syms Strategic Group (SSG) is seeking a talented Automated Test Engineer (Edifecs)
Added 1 min ago
Software Developer in Test (SDET)
Syms Strategic Group, LLC (SSG)
Charlottesville, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
Added 1 min ago
Senior Software Test Engineer
Syms Strategic Group, LLC (SSG)
Charlottesville, VA
Syms Strategic Group (SSG) is seeking a talented Senior Software Test Engineer
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MECM Engineer
CACI International
Chantilly, VA
CACI is looking for a skilled Microsoft Endpoint Management (MEM) Engineer, specializing in Microsoft Endpoint Configuration Manager (MECM, formerly SCCM) to support the Department of the…
Added 1 min ago
Solutions Architect, Cloud
National Student Clearinghouse
Herndon, VA
Added 1 min ago
Automated Test Engineer (Edifecs)
Syms Strategic Group, LLC (SSG)
Virginia Beach, VA
Syms Strategic Group (SSG) is seeking a talented Automated Test Engineer (Edifecs)
Added 1 min ago
Automated Test Engineer (MUMPS)
Syms Strategic Group, LLC (SSG)
Virginia Beach, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.
Added 1 min ago
Resident Engineer - Clinton/Nevada
State of Missouri
Clinton, MO
The resident engineer supervises contract administration and engineering personnel at a field office covering an area within a district and ensures surveying, inspection, documentation, and…
Added 1 min ago
Senior Software Test Engineer
Syms Strategic Group, LLC (SSG)
Virginia Beach, VA
Syms Strategic Group (SSG) is seeking a talented Senior Software Test Engineer
Added 1 min ago
Software Developer in Test (SDET)
Syms Strategic Group, LLC (SSG)
Virginia Beach, VA
If you have previously applied to Syms Strategic Group (SSG), there is no need to reapply. Applications are still under review.

Apple

Physical Design Engineer

Cupertino, CA, United States

$174,149 to $225,300 USD / year

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Job details

Pay: $174,149 to $225,300 USD / year
Working hours: 40 hours/week
Posting language: English
Posted: Nov 5, 2026

Original job description

Summary Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with logic design team to understand partition architecture and drive physical aspects early in design cycle; Complete netlist to GDS2 implementation for partition(s) meet schedule and design goals; Be responsible for timing, physical & electrical verification, driving the signoff closure for the partitions; Resolve design and flow issues related to physical design, identifying potential solutions and driving execution; Be a focal point for place and route, driving the work among place and route engineers, setting goals and milestones, planning short and long-term work, understanding dependencies between different domains like top, STA, block place and route; Work with physical design team, driving methodologies and "best known methods" to streamline physical design work, coming up with guidelines and checklists, driving execution, and tracking progress; Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors; Drive frontend and backend implementation from RTL to gds2, including synthesis, FV, floor planning, net listing, timing constraints, timing and power convergence, and ECO implementation; Be responsible for hands-on physical implementation and timing closure of core platforms and SoC's; Streamline the timing signoff criterions, timing analysis methodologies and flows and developing/enhancing ECO generation scripts for timing closure; Responsible for floor planning, physical synthesis, and physical design closure of large complex designs at 1GHz+ clock cycles; Drive physical design and timing convergence of high-frequency low-power at block level, cluster level, and/or full chip level. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications Master’s degree or foreign equivalent in Electrical, Electrical and Computer Engineering, or related field.

Experience and/or education must include:

Utilizing PNR tools like ICC, ICC2, or Innovus to be used for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for the design of partitions on SoCs. End-to-end understanding of digital design implementation fundamentals, logic modeling, and hardware description languages supporting digital IC design. Utilizing TCL, Perl, Python and Unix scripting to summarize data, improve execution efficiency and implement custom scripts to aid partition closure. Understanding of PD construction and analysis flow and methodologies to be able to successfully execute on, close and signoff partitions on SoCs. Understanding transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure and signoff of partitions on SoCs. Understanding digital logic and computer architecture fundamentals that build foundational knowledge of partitioning and resource planning in Integrated Circuits (ICs). Understanding results from Physical verification tools like calibre and generating fixes to address violations. Utilizing knowledge in signal behavior, interference effects, and noise reduction principles relevant to high-speed digital circuits.

Preferred Qualifications N/A

LMT Footer This position is not subject to the application limits.

EEO Statement Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

Accessibility At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Application Deadline Apple accepts applications to this posting on an ongoing basis.

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Skills

Place-and-route
Route
RTL
Computer engineering
Perl
Python
UNIX
Integrated circuits

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