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Added 7 hours ago
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Principal D2D SerDes & Analog Layout Design Engineer
Microsoft
CA · Mountain View, CA · Mountain View
- $142,800 to $304,200 USD / year
We are looking for a Principal D2D SerDes & Analog Layout Design Engineer to provide technical leadership for matching-critical analog layout and D2D SerDes physical implementation. This…
Added 10 hours ago
Software Development Engineer, SoC HAL
Annapurna Labs (U.S.) Inc.
Cupertino, CA
…learning how a hardware block works from its spec or from the engineer who designed it. You might add a feature to a driver, write tests for it, and work through code-review feedback, then…
Added 12 hours ago
RTL Engineer – Physical AI Solutions
Altera
San Jose, CA
As an RTL Engineer, you will be responsible for designing, implementing, and verifying high-performance digital logic that powers AI and accelerated computing solutions. You will…
Added 13 hours ago
Senior Electrical/Systems Engineer – High Power RF Systems
x Varian Medical Systems, Inc.
United States
We are looking for a motivated engineer or scientist to join our Beam Generation Group, which develops the radiation-producing subsystem at the heart of Varian Radiation Oncology machines.…
Added 15 hours ago
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Staff Control Systems Engineer, Safety & Interlock Systems
Thea Energy
Kearny, NJ
- $180,000 to $230,000 USD / year
…functions. Your work will span requirements, electrical and software design, hardware integration, testing, commissioning, and operational support. You will collaborate with controls…
Added 18 hours ago
Systems Engineer
Thea Energy
Kearny, NJ
Thea Energy is seeking for an experienced, organized, and motivated systems engineer. This position will work on an interdisciplinary team to integrate numerous first-of-a-kind technologies…
Added 22 hours ago
Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
Amazon
Cupertino, CA
…workloads in datacenters all around the world. As a Sr. SoC Power Engineer, you’ll contribute to the project at the ground level by modeling and estimating power at every stage of the…
Added 22 hours ago
Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
Amazon
Cupertino, CA
…workloads in datacenters all around the world. As a Sr. SoC Power Engineer, you’ll contribute to the project at the ground level by modeling and estimating power at every stage of the…
Added 1 day ago
Hardware/Software Co-Design Engineer, Inference
Google
Sunnyvale, CA
…behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its…
Added 1 day ago
Principal AI Platform and Model Operations Engineer - TS/SCI with Polygraph
GD Information Technology, Inc.
United States
We are seeking a hands-on AI Platform Operations Engineer to own and mature the end-to-end platform and lifecycle mechanisms that move AI models, prompts, retrieval assets, dependencies,…
Added 1 day ago
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Design Verification Engineer
Actalent
Santa Clara, CA
- $150,000 to $250,000 USD / year
We are seeking Design Verification Engineers to support the development of an advanced, high-performance SoC platform. This role will work across architecture, RTL, software, and systems…
Added 1 day ago
Lead GCP Engineer
Capgemini
Dallas, TX, TX
Ability to lead technical design discussions perform code reviews and mentor engineering teams
Added 1 day ago
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Design Engineering Architect – Systems and Interfaces
Cadence
United States
- $185,500 to $344,500 USD / year
The SSG Central Applications Engineering team seeks an experienced SoC design engineer to enable the integration and deployment of Cadence IP in complex customer system designs. As a Design…
Added 1 day ago
Staff Control Systems Engineer
Thea Energy
Kearny, NJ
Thea Energy is seeking a Staff Control Systems Engineer to design, develop, integrate, and test control, instrumentation, and data acquisition systems for the Integrated Eos Stellarator.…
Added 1 day ago
ASIC Engineering Intern, Formal Verification
Meta
Sunnyvale, CA
Meta is seeking an ASIC Engineer Intern, Formal Verification to join our Infrastructure Silicon organization. Our servers and data centers are the foundation upon which our rapidly scaling…
Added 2 days ago
Design Verification Engineer - Accelerators
Meta
Redmond, WA
Design Verification Engineer - Accelerators Responsibilities:
Added 2 days ago
Senior Accelerator Engineer, Cloud AI/ML server team
Amazon
Denver, CO
Experience in developing functional specifications, design verification plans and functional test procedures
Added 2 days ago
Senior Staff Software Engineer, AI/ML, Google Cloud Compute Infrastructure
Google
Sunnyvale, CA
…behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its…
Added 2 days ago
PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
Annapurna Labs (U.S.) Inc.
Austin, TX · Cupertino, CA
…Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed…
Added 2 days ago
Senior Engineer, SoC HAL
Annapurna Labs (U.S.) Inc.
Austin, TX · Cupertino, CA
…working through a hardware interface question with an RTL or design verification engineer, and shaping the architecture for a block still being designed. You might debug a failure spanning…
Added 2 days ago
Hardware Systems Technical Lead
Lightmatter
Mountain View, CA
We are looking for a talented engineer to provide technical leadership to the Hardware Systems organization to help us build the next generation of silicon photonics based artificial…
Added 2 days ago
Lead Avionics Survivability Engineer
Relativity Space
Long Beach, CA
As the Lead Avionics Survivability Engineer, you will lead the survivability team responsible for ensuring Terran R's electrical and electronic systems can withstand the harsh environments…
Added 2 days ago
Forward Deployment Engineer - Managing Business Architect
Capgemini
Atlanta, GA
We are seeking a Forward Deployment Engineer (FDE) - the tip of the spear for deploying AI-native solutions into live client environments. Working at the intersection of engineering,…
Added 3 days ago
RTL Design Engineer, TPU Compute
Google
Sunnyvale, CA
Knowledge of processor design, accelerators, or memory hierarchies.
Added 3 days ago
TPU Compute RTL Design Engineer
Google
Sunnyvale, CA · Austin, TX
Knowledge of processor design, accelerators, or memory hierarchies.

Annapurna Labs (U.S.) Inc.

Software Development Engineer, SoC HAL

Cupertino, CA, United States

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Job details

Posting language: English
Posted: Nov 6, 2026

Original job description

Description

Annapurna Labs builds the custom silicon at the heart of AWS machine learning servers, and we are hiring a software engineer to help build the Hardware Abstraction Layer (HAL) that brings these chips to life. If you love working where hardware meets software, writing the code that boots, configures, and debugs some of the largest custom silicon in the world, this is your team.

As a Software Engineer on the SoC HAL team, you will write and test C++ for the driver stack across the hardware blocks that make up our chips, learn how the silicon works from the engineers who design it, and grow your skills on a small, fast-moving team inside a large organization. No machine learning background is required (you will pick up ML concepts from colleagues if you want to). This role is based in Cupertino, CA.

Key job responsibilities Implement, test, and maintain HAL/driver features for individual hardware blocks (for example PCIe, DDR / HBM memory, DMA, system fabric, interrupt controllers, and boot / firmware), working from designs and interfaces set by more senior engineers.

Write clean, well-tested C++ and contribute to the team's test, code-review, and continuous-deployment practices.

Debug failures that span software and silicon, with support from the team, and build an understanding of how the HAL interacts with the hardware underneath it.

Learn the hardware/software interface by partnering with RTL and design verification engineers on well-scoped questions.

Provide feature additions and bug fixes on current and prior chips.

A day in the life A typical day moves between writing and reviewing C++ for the HAL, pairing with a teammate on a tricky bug, and learning how a hardware block works from its spec or from the engineer who designed it. You might add a feature to a driver, write tests for it, and work through code-review feedback, then dig into a failure that spans software and silicon. Your teammates are the HAL engineers you build alongside; the hardware design, verification, and firmware teams are close partners you will learn from; and your customers are the internal software teams that rely on the HAL to boot, configure, and debug the chip.

About the team Annapurna Labs designs and deploys some of the largest custom silicon in the world, including the Trainium and Inferentia machine learning accelerators. Our SoC HAL team builds the low-level software that boots, configures, and manages these chips, sitting between the hardware and the system software that runs the server. We are a small team that works closely with hardware, holds a high engineering bar, and invests in helping engineers grow. Based in Cupertino, CA, we value mentorship, clear written design, and software that outlasts any single chip. Basic qualifications

Knowledge of programming languages such as C/C++, Python, Java or Perl
Experience (non-internship) in professional software development, or currently enrolled in or recently completed a Bachelor's or Master's degree in computer science or a related field
Experience with data structures, algorithms, and software design fundamentals Preferred qualifications
Bachelor's degree or above in Computer Science, Computer Engineering, or related fields at time of application
Coursework, internship, or project experience in computer architecture or operating systems
Experience with C or C++ and object-oriented design
Exposure to low-level, embedded, or hardware-adjacent programming
Familiarity with testing, debugging, source control, and build processes in a team setting

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The starting pay for this position is listed below. Starting Day 1 of employment, Amazon offers EAP, Mental Health Support, Medical Advice Line, 401(k) matching. Learn more about our benefits at https://hiring.amazon.com/why-amazon/benefits.

Cupertino, CA, USA - 148,400.00 USD Annually

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