Job Details:
Job Description:
About the Role Altera is seeking a Software Architect, Software Simulation Infrastructure to define and drive the architecture of scalable, high-performance simulation platforms supporting next-generation FPGA and SoC products.
In this role, you will establish the technical vision and roadmap for software-based and hybrid simulation infrastructure used by architecture, firmware, software, design verification, and silicon validation teams. You will architect reusable, transaction-accurate modeling frameworks and integrated simulation environments that enable earlier software development, rapid architectural exploration, verification acceleration, and efficient full-chip bring-up.
This is a highly technical individual contributor role with broad organizational influence. You will partner closely with hardware architecture, RTL design, design verification, firmware, software, emulation, and validation teams to translate product requirements into robust simulation capabilities that scale across programs and product generations.
Key Responsibilities:
Responsibilities of the Principal Architect, Software Simulation Infrastructure include but are not limited to:
- Define the architectural vision, technical roadmap, and long-term strategy for Altera’s software simulation infrastructure across FPGA and SoC product development.
- Architect modular, extensible, and reusable C/C++-based simulation and modeling frameworks that support architectural exploration, firmware and software development, design verification, and system validation.
- Drive development of transaction-accurate and performance-aware models for complex SoC subsystems, including compute, memory, interconnect, I/O, and accelerator architectures.
- Establish approaches for integrating software models with RTL, testbenches, emulation, and full-chip simulation, including model substitution and comparison methodologies.
- Define performance strategy for simulation platforms, including profiling, optimization, compilation acceleration, parallelization, and efficient execution on developer and CI infrastructure.
- Collaborate with architecture teams to model and evaluate design tradeoffs involving performance, bandwidth, latency, buffering, routing, power, and scalability.
- Partner with firmware and software teams to enable early development, unit testing, regression testing, debug, and continuous integration before silicon availability.
- Work with design verification teams to align model behavior, interfaces, checking strategies, and validation criteria with RTL and subsystem verification plans.
- Establish software engineering standards for modeling infrastructure, including APIs, versioning, test strategy, code quality, documentation, release management, and maintainability.
- Lead technical reviews, evaluate architectural alternatives, resolve complex cross-functional issues, and make recommendations that balance product needs, schedule, quality, and long-term platform strategy.
- Mentor and provide technical leadership to engineers developing models, simulation frameworks, and infrastructure across multiple product teams.
- Identify and evaluate emerging simulation, emulation, virtualization, compiler, and AI-assisted development technologies that can improve engineering productivity and product quality.
Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $330,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications
- Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
- 12+ years of relevant industry experience in software modeling, simulation infrastructure, architecture, design verification, firmware, or semiconductor systems development.
- 8+ years of hands-on experience designing and developing software-based models, simulation frameworks, or verification infrastructure for complex ASIC, SoC, FPGA, networking, compute, or accelerator products.
- Expert-level C/C++ programming skills and strong proficiency with Python and Linux/Unix development environments.
- Demonstrated experience architecting transaction-level, functional, or performance models that enable software development, architectural analysis, and/or RTL verification.
- Experience integrating software models with RTL simulation, UVM/SystemVerilog environments, emulation, or other hardware verification and validation flows.
- Strong understanding of computer architecture and SoC design, including memory systems, interconnects, DMA, I/O, and performance analysis.
- Proven ability to lead complex technical initiatives and influence cross-functional teams spanning architecture, design, verification, firmware, software, and validation.
- Strong communication skills, with the ability to translate complex technical concepts into clear architecture, design, and execution plans.
Preferred Qualifications
- Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
- Experience developing simulation platforms that support multiple chip programs or product generations from a common codebase.
- Experience with SystemC, UVM, SystemVerilog, or comparable hardware modeling and verification methodologies.
- Experience applying compiler technologies, JIT compilation, LLVM, or other code-generation approaches to improve simulation performance.
- Experience with network processors, programmable logic, coherent interconnects, packet processing, cryptography accelerators, or high-bandwidth SoC fabrics.
- Experience with CI/CD systems, software regression infrastructure, source control, code review, and large-scale developer workflows.
- Experience leading or mentoring simulation, modeling, architecture, or verification engineers in a technically complex product environment.
Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
