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Added 3 mins ago
Senior Manager, Software Development Engineering
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Advanced Micro Devices, Inc

Packaging Integration Engineer

San Jose, CA, United States

Apply on careers.amd.com About employer

Applications open in a new tab.

Job details

Apply by: Nov 13, 2027
Posting language: English
Posted: Nov 13, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

Advanced packaging is at the center of some of the most important innovation happening in semiconductors today. AI accelerators, next-generation FPGAs, embedded SoCs, and custom ASICs are pushing the limits of package performance, integration, power delivery, thermal management, reliability, and manufacturability. AECG Packaging is where those challenges come together.

As a Packaging Integration Engineer, you’ll help turn complex silicon, package, and board requirements into manufacturable, reliable solutions. You’ll work across packaging technology, package design and electrical engineering, thermal-mechanical engineering, SI/PI, quality, reliability, and external manufacturing partners to drive technical decisions from concept through qualification and product readiness.

This is an opportunity for an engineer who enjoys solving multidisciplinary problems, influencing decisions across functional boundaries, and seeing advanced packaging solutions move from design trade-offs to real products.

THE PERSON:

You’re a hands-on, systems-minded engineer who can connect the dots across silicon, package, board, manufacturing, and reliability. You are comfortable working through ambiguity, bringing the right experts together, and driving technical issues to closure rather than allowing gaps to remain between organizations.

You communicate clearly with engineering teams, suppliers, and customer-facing stakeholders, and you can explain the trade-offs among performance, cost, manufacturability, reliability, and schedule. You combine technical depth with practical judgment, collaboration, and strong follow-through.

KEY RESPONSIBILITIES:

Lead DFM, DFMEA, and related manufacturability and risk reviews for advanced package solutions.
Drive packaging supply qualification in partnership with OSAT, substrate, and materials suppliers to deliver manufacturable, reliable, application-ready solutions.
Coordinate cross-functional engineering discussions spanning silicon design, packaging, SI/PI, thermal-mechanical engineering, quality, and reliability testing.
Drive issue resolution, align technical decisions, and track actions and commitments through genuine closure to keep programs on schedule.
Bridge gaps between functional teams and help integrate silicon, package, and PCB requirements into cohesive system-level solutions.
Evaluate technical trade-offs across performance, cost, manufacturability, reliability, and schedule, and communicate recommendations clearly to engineering and customer stakeholders.

PREFERRED EXPERIENCE:

Demonstrated experience in semiconductor packaging technology integration, including advanced 2.5D/3D integration and IC-package-PCB co-design or co-development.
Strong working knowledge of DFM, DFMEA, PFMEA, and packaging supply qualification with OSAT, substrate, and materials partners.
Experience with package design and analysis platforms such as Cadence, Synopsys, Ansys, AutoCAD, or equivalent EDA tools.
Experience with signal integrity and power integrity (SI/PI) analysis across package and board interconnects.
Understanding of high-speed I/O design considerations at the package level, including DDR or other memory-interface routing, timing, and packaging constraints.
Experience with power planes and power delivery network (PDN) optimization across silicon, package, and board.
Familiarity with UCIe (Universal Chiplet Interconnect Express) and other die-to-die or chiplet interconnect standards.
Ability to assess multidisciplinary design trade-offs and communicate recommendations effectively across engineering, supplier, and customer-facing teams.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree in Electrical Engineering, Materials Engineering, Mechanical Engineering, Semiconductor Engineering, or a related field is preferred.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Apply on careers.amd.com About employer

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Jobs in the United States