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Actalent

Senior PCB Layout Engineer

Waukesha, WI, United States

$50 to $75 USD / hour

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Job details

Pay: $50 to $75 USD / hour
Experience: At least 8+ years of professional PCB layout experience, including a minimum of 2+ years of proficiency with current versions of Cadence Allegro PCB Editor.
Posting language: English
Posted: Nov 2, 2026

Original job description

Job Title: Senior PCB Layout EngineerJob DescriptionThis role focuses on owning the high-speed printed circuit board layout for an Intel-based compute platform, taking complex designs from schematic handoff through fabrication release using Cadence Allegro. You will collaborate closely with hardware, signal integrity, mechanical, and manufacturing teams to deliver robust, manufacturable, high-density boards that meet demanding performance, reliability, and quality requirements.

Responsibilities

Lead the placement, stackup definition, routing, and release of complex, high-density, high-speed printed circuit boards using Cadence Allegro.
Implement and verify high-speed interfaces, including DDR5/LPDDR5 and PCIe Gen4/Gen5, to meet design-rule and signal integrity requirements.
Partner with hardware and signal integrity/power integrity engineers to develop constraints, perform pre- and post-layout simulations, and design power delivery networks.
Define PCB stackups and material selections in collaboration with fabrication vendors, balancing performance, cost, reliability, and long-term availability.
Manage BGA fanout and breakout strategies, including via-in-pad, blind and buried vias, and HDI techniques.
Create and maintain PCB library footprints and padstacks to IPC-7351 standards in coordination with the component library process.
Produce complete manufacturing documentation packages, including Gerber/ODB++ files, drill files, assembly drawings, fabrication notes, and support DFM, DFA, and DFT reviews with fabricators and contract assemblers.
Support board bring-up, debug, and respin activities through structured design change control and revision management.
Maintain accurate design archives and documentation in alignment with ISO 9001 and related quality system requirements.
Contribute to the development and refinement of layout standards, design guidelines, and best practices for the engineering team.

Essential Skills

At least 8+ years of professional PCB layout experience, including a minimum of 2+ years of proficiency with current versions of Cadence Allegro PCB Editor.
Demonstrated experience laying out high-performance processor platforms with BGA packages and multi-gigabit interfaces.
Strong working knowledge of high-speed design principles, including impedance control, length and skew matching, differential pair routing, return path management, and crosstalk mitigation.
Experience with constraint-driven design using Allegro Constraint Manager.
Working knowledge of relevant IPC standards and their application in PCB layout and fabrication.
Proven ability to deliver complete, manufacturable release packages and work directly with PCB fabricators and contract assemblers.
Solid understanding of power integrity and thermal considerations as they relate to PCB layout.
Associate's or bachelor's degree in electrical or electronics engineering technology, or equivalent practical experience.
Hands-on experience with Cadence Allegro for layout design of complex PCBs, including HDI boards.
Experience supporting board bring-up and debug activities in collaboration with cross-functional engineering teams.

Additional Skills & Qualifications

Experience implementing and verifying USB, DisplayPort/HDMI, and Ethernet interfaces to meet design-rule and signal integrity requirements.
Experience with HDI technology, high-layer-count boards (12+ layers), and advanced stackup design.
Background in designing for defense, aerospace, or other high-reliability applications, including familiarity with rugged design practices such as shock, vibration, thermal management, and conformal coating, as well as IPC Class 3 requirements.
Familiarity with DO-160, MIL-STD-810, and MIL-STD-461 design considerations and related documentation requirements.
Understanding of AS9100 quality expectations and configuration control processes for defense and aerospace deliverables.
Eligibility to work with export-controlled information (ITAR/EAR) for certain programs, as applicable.
Experience with Intel client or embedded platform reference designs, including use of Intel design guides and collaboration with Intel field engineering resources.
Familiarity with Cadence Sigrity or other signal integrity and power integrity tools.
Experience with Allegro database and library management tools.
IPC CID or CID+ certification.
Strong problem-solving skills and attention to detail in a fast-paced, engineering-driven environment.
Ability to communicate clearly with cross-functional teams, vendors, and manufacturing partners.

Work EnvironmentThis position is based in an office environment with on-site presence expected to support a hands-on engineering role. You will primarily perform computer-based design work using tools such as Cadence Allegro and related SI/PI software, with occasional lab time for board bring-up, debug, and validation. The role may involve limited travel to fabrication and assembly partners, as well as to customer or supplier sites, to support manufacturing reviews, issue resolution, and technical collaboration. The environment emphasizes structured quality systems, including adherence to ISO 9001 processes, and collaboration across hardware, signal integrity, mechanical, and manufacturing disciplines. Job Type & LocationThis is a Contract to Hire position based out of Waukesha, WI. Pay and BenefitsThe pay range for this position is $50.00 - $75.00/hr. Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits

available for this temporary role may include the following:

Medical, dental & vision Critical Illness, Accident, and Hospital 401(k) Retirement Plan Pre-tax and Roth post-tax contributions available Life Insurance (Voluntary Life & AD&D for the employee and dependents) Short and long-term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time Off/Leave (PTO, Vacation or Sick Leave) Job Type & LocationThis is a Contract to Hire position based out of Waukesha, WI. Application DeadlineThis position is anticipated to close on Nov 16, 2026. Workplace TypeThis is a fully remote position.About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.

San Francisco Fair Chance Ordinance:

Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector:

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI):

We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.

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