Design Verification Engineer

Description

Design Verification Engineer Role Overview We are seeking Design Verification Engineers to support the development of an advanced, high-performance SoC platform. This role will work across architecture, RTL, software, and systems engineering to validate complex digital IP and full-chip functionality. You will be responsible for ensuring the design meets functional, performance, reliability, and system requirements, from individual hardware blocks through full hardware/software integration. This is a strong opportunity for engineers who enjoy debugging complex systems, identifying corner cases, and working across multiple areas of SoC development.

Responsibilities

Develop verification plans and strategies for complex SoC blocks and subsystems. Build and maintain verification environments using SystemVerilog, UVM, C/C++, assertions, coverage methodologies, and formal verification techniques. Partner with architects and RTL engineers to establish coverage targets, test plans, and functional requirements. Verify areas such as compute engines, memory subsystems, caches, interconnects, processors, DMA, and control logic. Perform hardware/software co-verification involving firmware, drivers, runtime software, and operating system interactions. Validate performance, latency, bandwidth, QoS, and real-time behavior across different workloads. Develop assertions, scoreboards, checkers, testbenches, and verification automation. Support emulation, FPGA-based validation, and pre-silicon software development. Investigate failures and perform root-cause analysis across hardware and software. Support post-silicon debug and system-level issue resolution. Improve verification efficiency through automation and modern engineering tools. Required Qualifications Experience in digital design verification for complex ASIC or SoC designs. Strong knowledge of SystemVerilog and UVM. Experience with verification programming or modeling using C/C++. Understanding of computer architecture, microarchitecture, and digital design fundamentals. Experience with assertions, functional coverage, constrained-random verification, and coverage closure. Familiarity with formal verification methodologies. Knowledge of one or more areas such as processors, accelerators, caches, memory systems, interconnects, or DMA architectures. Strong debugging and root-cause analysis skills. Ability to collaborate across architecture, design, software, and systems teams. Preferred Qualifications Experience with functional safety standards such as ISO 26262, IEC 61508, IEC 61511, or ISO 13849. Background working with AI/ML accelerators or edge-compute silicon. Experience with robotics, autonomous platforms, industrial systems, or other embedded compute environments. Experience validating real-time, latency-sensitive, or QoS-driven systems. Background in hardware/software co-verification or system-level validation. Familiarity with performance analysis, profiling, or workload characterization. Experience with emulation or FPGA prototyping. Relevant experience may come from areas including CPUs, GPUs, AI accelerators, networking silicon, storage, automotive/ADAS, robotics, aerospace/defense, or safety-critical computing.

Skills

Design verification, Verilog, Design

Top Skills Details

Design verification,Verilog

Experience Level

Intermediate Level

Job Type & LocationThis is a Permanent position based out of Santa Clara, CA. Pay and BenefitsThe pay range for this position is $150000.00 - $250000.00/yr. Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits

available for this role may include the following:

Medical, dental & vision Critical Illness, Accident, and Hospital 401(k) Retirement Plan Pre-tax and Roth post-tax contributions available Life Insurance (Voluntary Life & AD&D for the employee and dependents) Short and long-term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time Off/Leave (PTO, Vacation or Sick Leave) Job Type & LocationThis is a Permanent position based out of Santa Clara, CA. Application DeadlineThis position is anticipated to close on Nov 18, 2026. Workplace TypeThis is a fully onsite position in Santa Clara,CA.About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

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